This invention is in the field of semiconductor integrated circuits, and is more specifically directed to integrated structures for protecting such circuits from electrostatic discharge events.
Modern high-density integrated circuits are known to be vulnerable to damage from the electrostatic discharge (ESD) of a charged body (human or otherwise) as it physically contacts an integrated circuit. ESD damage occurs when the amount of charge exceeds the capability of the conduction path through the integrated circuit. The typical ESD failure mechanisms include thermal runaway resulting in junction shorting, and dielectric breakdown resulting in gate-junction shorting (e.g., in the metal-oxide-semiconductor, or MOS, context).
To avoid damage from ESD, modern integrated circuits incorporate ESD protection devices, or structures, at each external terminal. ESD protection devices generally operate by providing a high capacity conduction path, so that the brief but massive ESD charge may be safely conducted away from circuitry that is not capable of handling the event. In some cases, ESD protection is inherent to the particular terminal, as in the case of a power supply terminal, which connects to an extremely large p-n junction capable of absorbing the ESD charge. Inputs and outputs, on the other hand, typically have a separate ESD protection device added in parallel to the functional terminal. The ideal ESD protection device turns on quickly in response to an ESD event to safely and rapidly conduct the ESD charge, but remains off and presents no load during normal operation.
Examples of ESD protection devices are well known in the art. In the case of MOS technology, an early ESD protection device was provided by a parasitic thick-field oxide MOS transistor that was turned on by and conducted ESD current, as described in U.S. Pat. No. 4,692,781 and in U.S. Pat. No. 4,855,620, both assigned to Texas Instruments Incorporated and incorporated herein by this reference. As the feature sizes of MOS integrated circuits became smaller, and with the advent of complementary MOS (CMOS) technology, the most popular ESD protection devices utilized a parasitic bipolar device to conduct the ESD current, triggered by way of a silicon-controlled-rectifier (SCR) structure, as described in Rountree et al., “A Process-Tolerant Input Protection Circuit for Advanced CMOS Processes”, 1988 EOS/ESD Symposium, pp. 201-205, incorporated herein by this reference, and in U.S. Pat. No. 5,012,317 and U.S. Pat. No. 5,907,462, both assigned to Texas Instruments Incorporated and also incorporated herein by this reference.
FIG. 1 illustrates an integrated circuit including conventional ESD protection circuits and structures, in which external terminals are protected from damage due to electrostatic discharge relative to device substrate ground. As shown in FIG. 1, external terminals PIN1, PIN2 serve as inputs, outputs, or both, for functional circuitry 10. External terminal GND is typically connected to the substrate of the integrated circuit, which serves as device ground. Those skilled in the art will understand that external terminals PIN1, PIN2, GND may be physically realized in various ways. Typically, these external terminals include a bond pad on the surface of the integrated circuit chip itself, which is connected by way of a bond wire or lead frame to an external terminal of the device package (such as a package pin, a package pad for surface mount packages, or a solder bump) or which is soldered directly to a land of a circuit board or multichip substrate. In any event, terminals PIN1, PIN2, GND are electrically connected outside of the integrated circuit to communicate signals or to receive a bias voltage, and as such are capable of receiving an electrostatic discharge.
In this conventional arrangement, the electrostatic discharge (ESD) from terminals PIN1, PIN2 to device ground GND is safely conducted by way of n-p-n transistors 4A, 4B, respectively. Referring to the example of the protection circuit for terminal PIN1, n-p-n transistor 4A has its collector connected to terminal PIN1 and its emitter connected to substrate ground GND, effectively in parallel with functional circuitry 10. Trigger 6A and resistor 7A are connected in series between terminal PIN1 and substrate ground GND, and the base of transistor 4A is connected to the node between trigger circuit 6A and resistor 7A. Typically, trigger 6A corresponds to a device or element that defines the turn-on of transistor 4A. In some cases, trigger 6A is not a particular component (i.e., simply a connection), in which case transistor 4A turns on when its base-collector junction breaks down (at a voltage BVcbo) in response to a positive polarity ESD event. In another example, trigger 6A may be a capacitor, or an element such as a Zener diode that breaks down at a voltage that is exceeded by a significant positive polarity ESD event, with the voltage drop across resistor 7A due to this current forward-biasing the base-emitter junction of transistor 4A. Alternatively, this ESD protection scheme may instead involve a field effect device as transistor 4A, for example an n-channel MOSFET, as known in the art. In any case, transistor 4A safely conducts the ESD energy through a low-impedance path to substrate ground GND, ensuring that damaging densities of energy are not conducted through functional circuitry 10. During normal device operation, assuming a sufficiently high trigger voltage, transistors 4A, 4B remain off, and thus do not affect the operation of the integrated circuit.
Protection for negative polarity ESD events at terminals PIN1, PIN2 is provided by diodes 5A, 5B, respectively. Typically, diodes 5A, 5B are simply the parasitic diodes between the n-type region serving as the collector of transistors 4A, 4B and the p-type substrate. Diodes 5A, 5B are each forward-biased by negative ESD events at terminals PIN1, PIN2, respectively, so that the ESD energy is safely conducted through this low-impedance path. In normal operation, substrate ground GND is at a sufficiently low voltage relative to the specified voltages at terminals PIN1, PIN2 that these diodes 5A, 5B remain reverse-biased, and do not affect the voltage levels at terminals PIN1, PIN2 nor the operation of functional circuitry 10.
Some types of modern integrated circuits require ESD protection not only between terminals PIN1, PIN2 and substrate ground GND, but also require protection for ESD events between any given pair of its signal terminals (e.g., between terminals PIN1 and PIN2), not involving substrate ground GND. These types of circuits include so-called mixed signal integrated circuits, which include both digital and analog functions. Examples of such mixed signal devices include charge-pump circuits, voltage regulator circuits, boot-strap or “flying” gate drivers, and the like. FIG. 2 illustrates such an integrated circuit having a conventional ESD protection circuit between terminals PIN1, PIN2.
In this example, n-p-n transistor 4C has its collector connected to terminal PIN1 and its emitter connected to terminal PIN2. Trigger 6C and resistor 7C are also connected in series between terminals PIN1, PIN2, and the base of transistor 4C is connected to the node between trigger circuit 6C and resistor 7C. These devices protect functional circuitry 10 from damage due to ESD events of positive polarity at terminal PIN1 relative to terminal PIN2.
However, parasitic diode 5C at the collector of transistor 4C is not coupled to terminal PIN2, but instead is connected to the substrate, at substrate ground GND. As such, in the event of a negative polarity ESD event at terminal PIN1 relative to terminal PIN2, the voltage at which terminal PIN1 is clamped by either the series combination of structure 5C and structure 4B, or the structure of transistor 4C, will be higher than desirable for effective ESD protection performance. Instead, protection for negative polarity pin-to-pin ESD events is provided by isolated diode 15C, having its cathode at terminal PIN1 and its anode at terminal PIN2. Again, as in the case of FIG. 1, a negative polarity ESD event at terminal PIN1 relative to terminal PIN2 will forward bias isolated diode 15C, so that a low-impedance path for this energy will be provided, preventing damage to functional circuit 10.
Those skilled in the art having reference to this specification will realize that there is not a need to provide a mirror-image ESD structure between terminals PIN2, PIN1 (i.e., having an n-p-n transistor with its collector at terminal PIN2 and its emitter at PIN1). Rather, the circuit of FIG. 2, including isolated diode 15C, is capable of protecting both terminals PIN1, PIN2 in either direction.
The orientation of the ESD structure (specifically isolated diode 15C) between signal terminals PIN1, PIN2 should take into account situations in which functional circuitry 10 may permit the voltage on one signal terminal (e.g., PIN1) to exceed the voltage on another signal terminal (e.g., PIN2) in normal operation. In addition, as conventional in the art, similar ESD protection circuits are provided between each pair of terminals that are required to have such protection.
While the arrangement of FIG. 2 provides excellent ESD protection for all combinations of ESD events, conventional implementations of the pin-to-pin protection, particularly in providing the additional isolated diode 15C as shown in FIG. 2, have been inefficient in practice. FIG. 3 illustrates the conventional physical implementation of the pin-to-pin ESD protection circuit illustrated in FIG. 2, in a cross-sectional view.
In the conventional example illustrated in FIG. 3, the integrated circuit is formed into lightly-doped p-type substrate 30. N-type buried layer 32 is a heavily doped n-type region that underlies a portion of the surface of substrate 30, and provides a subcollector for n-p-n transistor 4C. The collector of transistor 4C is provided by n-well 34, disposed above n-type buried layer 32, and the base of transistor 4C is p-type region 36 that is diffused into n-well 34 from the surface. The emitter of transistor 4C is implemented by n+ region 38 diffused into p-region 36; n+ region is connected to signal terminal PIN2 by a metal conductor (not shown). P+ region 40 is also disposed within p-region 36, and is connected to signal terminal PIN2 by way of resistor 7C, typically a polysilicon or a diffused resistor, and a corresponding metal conductor (not shown). The subcollector at n-type buried layer 32 is connected to signal terminal PIN1 by way of buried contact 44 (typically a heavily doped buried region), overlying n+ region 42, and a corresponding metal conductor (not shown).
In this example, trigger 6C is simply the connection to collector region 42 and collector region 42 itself. A positive ESD event of sufficient energy between signal terminals PIN1, PIN2 will break down the collector base junction of transistor 4C. The breakdown current will flow into the base of transistor 4C, and to signal terminal PIN2 through resistor 7C, forward biasing the emitter-base junction and initiating bipolar conduction. Once transistor 4C is turned-on, collector-emitter current will be safely conducted from signal terminal PIN1 through n+ region 42, buried contact 44, n-type buried layer 32, n-well 34, p-type region 36, and n+ region 38.
In this conventional arrangement, negative polarity ESD events are handled by isolated diode 15C. Isolated diode 15C has an anode formed by p+ region 48 that is disposed within n-well 46, and a cathode formed by n+ region 50, also within n-well 46. P+ region 48 and n+ region 50 are connected to signal terminals PIN2, PIN1, respectively, by conventional metal conductors (not shown). Parasitic diode 5C is provided between n+ region 50 and n-well 46, and p-type substrate 46. In this arrangement, a negative polarity ESD event at signal terminal PIN1 relative to signal terminal PIN2 will forward bias isolated diode 15C, which safely conducts the ESD energy between these signal terminals.
However, in this conventional arrangement as shown in FIG. 3, the second instance of n-well 46 that is provided for isolated diode 15C occupies a large amount of silicon area. In particular, conventional integrated circuits typically have a design rule that specifies the minimum acceptable spacing between adjacent n-wells, primarily to avoid punch-through. In the example of FIG. 3, this well-to-well spacing between adjacent n-wells 34, 46 is illustrated by distance WW. A typical specification for distance WW in a conventional mixed signal device having high voltage capability is 15 to 20 μm. Especially considering that a corresponding isolated diode 15C is required between each pair of signal terminals in the device, the area required for the diode and the well-to-well spacing can become significant.